The present invention relates to a semiconductor package, and more particularly, to a substrate for a semiconductor package, a semiconductor package including the same, and a stack package using the semiconductor package, which can prevent the manufacturing yield from decreasing and the overall thickness of a semiconductor package from increasing due to the use of wires.
In the semiconductor industry, packaging technology for integrated circuits has continuously been developed to satisfy the demand toward miniaturization and mounting reliability. For example, the demand for miniaturization has expedited the development of techniques for a package having a size approaching that of a chip, and the demand for mounting reliability has highlighted the importance of packaging techniques for improving the efficiency of mounting work and mechanical and electrical reliability after mounting.
As miniaturization and high performance are demanded in electric and electronic products, various techniques for providing a semiconductor module of high capacity have been researched and developed. A method for providing a semiconductor module of high capacity includes high integration of a memory chip. High integration of a memory chip can be accomplished by integrating an increased number of cells in a limited space of the semiconductor chip.
However, high integration of a memory chip requires high precision techniques, such as a fine line width, and a lengthy development period. Under these situations, a stacking technique has been suggested as another method for providing a semiconductor module of high capacity.
The stacking technique is divided into a method of embedding two stacked chips in one package and a method of stacking two separate packages which are independently packaged.
However, the method of stacking two separate packages cannot accommodate the trend toward miniaturization of electric and electronic products, and has limitations in that the overall thickness of a realized stack package is substantial. Therefore, recently, research for realizing a stack package or a multi-chip package by embedding at least two semiconductor chips in one package has actively been made.
In this regard, in the conventional art, while not illustrated in a drawing, various problems are caused as described below, due to the fact that metal wires are used to electrically connect a substrate and respective stacked semiconductor chips.
First, since a wire bonding process should be individually conducted every time when stacking a semiconductor chip, UPN (units per hour) decreases, and the total manufacturing cost increases due to the number of wires to be used and the number of bonding processes to be conducted.
Second, as the thickness of semiconductor chips gradually decreases, defects such as bouncing and cracks due to the warpage of the semiconductor chips can occur when conducting a wire bonding process, and wires are likely to be short-circuited due to a sweeping phenomenon of the wires when conducting a molding process.
Third, as the length of the wires increases depending upon the number of semiconductor chips to be stacked, difficulties exist in transmitting electric signals, and accordingly, limitations are caused in realizing a semiconductor package of a high density stack type.
Fourth, the overall thickness of a semiconductor package increases due to stacking of semiconductor chips on a substrate.